View NCP81233_8962206.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2017 march, 2017 ? rev. p1 1 publication order number: NCP81233/d NCP81233 product preview multi\phase controller with i 2 c interface for drmos the NCP81233, a multi-phase synchronous buck controller with an i 2 c interface, provides power management solutions for applications supported by drmos. it supports 1-, 2-, 3-, 4-, or 6-phase operation and provides differential voltage and current sense, flexible programming, and comprehensive protections. features ? selectable 1-, 2-, 3-, 4-, or 6-phase operation ? support up to 12-phase operation with phase doublers ? i 2 c interface with 8 programmable addresses ? vin = 4.5 v ~ 20 v with input feedforward ? integrated 5.35 v ldo and 3.3 v ldo ? fsw = 200 k ~ 1.2 mhz ? vout = 0.6 v ~ 5.3 v with 0.25 v~1.52 v dac (5 mv/step) ? programmable vboot voltage 0.6v ~ 1.23v (10mv/step) with restore function ? dvid slew rate options (0.125 mv/us, 0.25 mv/us, 0.5 mv/us, 1 mv/us, 2 mv/us, 4 mv/us, 8 mv/us, 16 mv/us) ? programmable external reference input ? pwm output compatible to 3.3 v and 5 v drmos ? differential output voltage sense ? differential current sense compatible for both inductor dcr sense and drmos iout signal ? programmable load line ? report of vout and iout ? enable with programmable input uvlo ? drmos power ready detection (drvon) ? externally programmable soft start ? power saving interface ? power good indicator ? programmable over current protection ? programmable over/under voltage protection ? hiccup over temperature protection ? thermal shutdown protection ? this is a pb-free device typical applications ? telecom applications ? server and storage system ? graphics card applications ? multiphase dc-dc power management this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. www.onsemi.com gfn52 6x6, o.4p case 485be 52 1 pinout 5 4 3 2 1 9 8 7 6 48 47 46 45 44 52 51 50 49 gnd 53 10 43 42 37 11 12 41 40 34 35 36 37 38 30 31 32 33 29 28 39 18 17 16 15 14 22 21 20 19 23 24 24 13 25 26 27 52 pin, qfn *this information is generic. please refer to device data sheet for actual part marking. pb-free indicator, ?g? or microdot ? ?, may or may not be present. a = assembly location wl = wafer lot yy = year ww = work week g = pb-free package NCP81233 awlyywwg for more details see figure 1. marking diagram* ordering information device package shipping ? NCP81233mntxg qfn52 (pb-free) 2500 / tape & reel ?for information on tape and reel specifications, in - cluding part orientation and tape sizes, please refe r to our tape and reel packaging specification s brochure, brd8011/d .
NCP81233 www.onsemi.com 2 figure 1. pin configuration pwm2 otp addr 5 4 3 2 1 sda fset 9 8 7 6 vboot2 vboot1 48 47 46 45 44 52 51 50 49 gnd 53 10 43 diffout comp fb alert# vdfb vdrp ss mode2 42 vsp vsn scl 11 12 imon cssum vref nc imax 41 ilmt 40 refin isn2 34 35 36 37 38 isp3 isn1 isn3 isp2 30 31 32 33 isp5 isn4 29 isp4 isn6 isn5 28 isp6 39 isp1 18 17 16 15 14 22 21 20 19 pwm3 pwm4 23 pwm6 vin en pwm5 vcc3v drvon pvcc vcc5v 24 25 13 pwm1 pgood 26 27 mode1 config
NCP81233 www.onsemi.com 3 ordering information table 1. pin description pin name type description 1 imon analog output out current monitor. provides output signal representing output current by connecting a capacitor from this pin to ground. 2 imax analog input current maximum. a resistor from this pin to ground programs imax. 3 vboot1 analog input boot-up voltage 1. a resistor from this pin to ground programs boot voltage 4 vboot2 analog input boot-up voltage 2. a resistor from this pin to ground programs boot voltage. 5 ss analog input soft-start slew rate. a resistor from this pin to ground programs soft-start slew rate. 6 fset analog input frequency selection. a resistor from this pin to ground programs switching frequency per phase. 7 config analog input configuration. a resistor from this pin to ground programs configuration of power stages. 8 mode1 analog input mode programming 1. a resistor from this pin to ground programs configuration of operation functions. 9 mode2 analog input mode programming 2. a resistor from this pin to ground programs configuration of operation functions. 10 addr analog input address. a resistor from this pin to ground programs address of i 2 c interface. 11 sda logic bidirectional serial data i/o port. data port of i 2 c interface. 12 alert# logic output alert. open-drain output. provides a logic low valid alert signal. 13 scl logic input serial clock. clock input of i 2 c interface. 14 pgood logic output power good. open-drain output. provides a logic high valid power good output signal, indicating the regulator?s output is in regulation window. 15 drvon analog input driver on. high input voltage means power supply of drmos?s driver is ready. 16 en analog input enable. logic high enables controller while logic low disables controller. input supply uvlo can be programmed at this pin. 17 vin power input power supply input. power supply input pin of the device, which is connected to the integrated 5.35 v ldo and 3.3 v ldo. 4.7 f or more ceramic capacitors must bypass this input to power ground. the capacitors should be placed as close as possible to this pin. 18 vcc5v analog power voltage supply of controller. output of integrated 5.35 v ldo and power input pin of analog circuits. a 4.7 f ceramic capacitor bypasses this input to gnd. this capacitor should be placed as close as possible to this pin. 19 vcc3v analog power 3.3 v voltage supply. output of integrated 3.3 v ldo. a 4.7 f ceramic capacitor bypasses this input to gnd. this capacitor should be placed as close as possible to this pin. 20 pvcc analog power voltage supply of pwm drivers. power supply input pin of internal pwm drivers and digital circuits, which is connected to vcc5 v via a 4.7 ? resistor. a 1 f or larger ceramic capacitor bypasses this input to ground. this capacitor should be placed as close as possible to this pin. 21 pwm6 analog output pwm 6. pwm output of phase 6. 22 pwm5 analog output pwm 5. pwm output of phase 5. 23 pwm4 analog output pwm 4. pwm output of phase 4. 24 pwm3 analog output pwm 3. pwm output of phase 3. 25 pwm2 analog output pwm 2. pwm output of phase 2. 26 pwm1 analog output pwm 1. pwm output of phase 1. 27 vb_rst# / psi logic input vboot restore. logic low restores output to boot voltage. power saving interface. logic high enables multi-phase ccm operation, and logic low enables 1-phase ccm operation. pin function is programmed at mode2 pin.
NCP81233 www.onsemi.com 4 table 1. pin description (continued) pin description type name 28 isp6 analog input current sense positive input 6. non-inverting input of differential current sense amplifier of phase 6. 29 isn6 analog input current sense negative input 6. inverting input of differential current sense amplifier of phase 6. 30 isn5 analog input current sense negative input 5. inverting input of differential current sense amplifier of phase 5. 31 isp5 analog input current sense positive input 5. non-inverting input of differential current sense amplifier of phase 5. 32 isp4 analog input current sense positive input 4. non-inverting input of differential current sense amplifier of phase 4. 33 isn4 analog input current sense negative input 4. inverting input of differential current sense amplifier of phase 4. 34 isn3 analog input current sense negative input 3. inverting input of differential current sense amplifier of phase 3. 35 isp3 analog input current sense positive input 3. non-inverting input of differential current sense amplifier of phase 3. 36 isp2 analog input current sense positive input 2. non-inverting input of differential current sense amplifier of phase 2. 37 isn2 analog input current sense negative input 2. inverting input of differential current sense amplifier of phase 2. 38 isn1 analog input current sense negative input 1. inverting input of differential current sense amplifier of phase 1. 39 isp1 analog input current sense positive input 1. non-inverting input of differential current sense amplifier of phase 1. 40 ilmt analog input limit of current. voltage at this pin sets over-current threshold. 41 otp analog input over temperature protection. voltage at this pin sets over-temperature threshold. 42 vref analog output output of reference. output of 0.6 v reference. a 10 nf ceramic capacitor bypasses this input to gnd. this capacitor should be placed as close as possible to this pin. 43 cssum analog output current sense sum. output of current sum amplifier. 44 vdfb analog output droop amplifier feedback. inverting input of droop amplifier 45 vdrp analog output droop amplifier output. output of droop amplifier. 46 nc no connection 47 comp analog output compensation. output pin of error amplifier. 48 fb analog input feedback. inverting input of internal error amplifier. 49 diffout analog output differential amplifier output. output pin of differential voltage sense amplifier. 50 vsp analog input voltage sense positive input. non-inverting input of differential voltage sense amplifier. 51 vsn analog input voltage sense negative input. inverting input of differential voltage sense amplifier. 52 refin analog input reference voltage input. external reference voltage input. 53 therm/gnd analog ground thermal pad and analog ground. ground of internal control circuits. must be connected to the system ground.
NCP81233 www.onsemi.com 5 figure 2. typical application circuit with programmed boot voltage vcc5v gnd 3v3 en pgood pwm1 fb NCP81233 comp isn1 diffout isp1 vin pwm vin vswh cgnd pgnd ncp5339 vin vou t vsn vsp en pgood ss fset addr vref otp ilmt vboot2 drvon drvon pvcc vb_rst# / psi vb_rst# sda alert# sda alert# scl scl pwm2 isn2 isp2 pwm3 isn3 isp3 pwm4 isn4 isp4 pwm5 isn5 isp5 pwm6 isn6 isp6 vboot1 mode1 mode2 config refin
NCP81233 www.onsemi.com 6 figure 3. typical application circuit with external reference input ref gnd 3v3 en pgood pwm1 fb NCP81233 comp isn1 diffout isp1 vin pwm vin vswh cgnd pgnd ncp5339 vin vou t vsn vsp en pgood ss fset addr vref otp ilmt vboot2 drvon drvon vb_rst# / psi psi sda alert# sda alert# scl scl pwm2 isn2 isp2 pwm3 isn3 isp3 pwm4 isn4 isp4 pwm5 isn5 isp5 pwm6 isn6 isp6 vboot1 mode1 mode2 config refin vcc5v pvcc
NCP81233 www.onsemi.com 7 figure 4. application circuit with phase doublers vou t pwm_in pwma cspa pwmb ncp81162 pwm vin vswh pgnd ncp5339 vin pwm vin vswh pgnd ncp5339 vin csna csnb cspb pwm1 isn1 isp1 pwm2 isp2 isn2 pwm3 isp3 isn3 pwm4 isp4 isn4 pwm5 isp5 isn5 pwm6 isp6 isn6 NCP81233 vccd
NCP81233 www.onsemi.com 8 figure 5. functional block diagram mode1 vcc5v gnd vref pgood imax diffout vin vsp vsn fset ldo reference programming detection vboot1 vboot2 uvlo & pgood en fb comp vbias otp over temperature protection ot drvon 3v3 ilmt pwm1 isp1 pwm2 dual?channel / multi?phase pwm control & protections pwm3 pwm4 isn1 cs1 isp2 isn2 cs2 isp3 isn3 cs3 isp4 isn4 cs4 current limit oc1 oc3 oc1 oc2 oc3 oc4 oc2 oc4 vdfb vdrp cssum i 2 c interface sda scl mode2 alert# vid dac / refin ?1/3 pvcc ilmt vref isp5 isn5 cs5 isp6 isn6 cs6 oc5 oc6 oc5 oc6 pwm5 pwm6 vb_rst# /psi imon vdrp vbias 10 ss addr refin
NCP81233 www.onsemi.com 9 table 2. maximum ratings rating symbol value unit min max power supply voltage to pgnd v vin 30 v supply voltage vcc5v to gnd v vcc5v ?0.3 6.5 v vsnx to gnd v vsn ?0.2 0.2 v other pins to gnd ?0.3 vcc5 v+0.3 v human body model (hbm) esd rating are (note 1) esd hbm 2500 v charge device model (cdm) esd rating are (note 1) esd cdm 2000 v latch up current: (note 2) i lu ?100 100 ma operating junction temperature range (note 3) t j ?40 125 c operating ambient temperature range t a ?40 100 c storage temperature range t stg ?55 150 c thermal resistance junction to top case(note 4) r jc 1.65 c/w thermal resistance junction to board (note 4) r jb 3.2 c/w thermal resistance junction to ambient (note 4) r ja 67.4 c/w power dissipation (note 5) p d 1.48 w moisture sensitivity level (note 6) msl 1 ? stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device is esd sensitive. handling precautions are needed to avoid damage or performance degradation. 2. latch up current per jedec standard: jesd78 class ii. 3. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 4. jedec standard jesd 51?7 (1s2p direct-attach method) with 0 lfm. it is for checking junction temperature using external measurement. 5. the maximum power dissipation (pd) is dependent on input voltage, maximum output current and external components selected. ta mbient = 25 c, tjunc_max = 125 c, pd = (tjunc_max?t_amb)/theta ja 6. moisture sensitivity level (msl): 1 per ipc/jedec standard: j-std-020a. table 3. electrical characteristics (v in = 12 v, typical values are referenced to t a = t j = 25 c, min and max values are referenced to t a = t j = ?40 c to 100 c. unless other noted.) characteristics test conditions symbol min typ max units supply voltage vin supply voltage range (note 7) v in 4.5 12 20 v vcc5v under-voltage (uvlo) threshold vcc5v falling v ccuv? 3.7 v vcc5v ok threshold vcc5v rising v ccok 4.3 v vcc5v uvlo hysteresis v cchys 270 mv vcc3v under?voltage (uvlo) threshold vcc3v falling v cc3uv? 2.6 v vcc3v ok threshold vcc3v rising v cc3ok 2.9 v vcc3v uvlo hysteresis v cc3hys 135 mv vcc5v regulator output voltage 6v < vin < 20v, ivcc5v = 15ma (external),en = low v cc 5.2 5.35 5.5 v load regulation ivcc5v = 5ma to 25ma (external), en = low ?2.0 0.2 2.0 % dropout voltage vin = 5v, ivcc5v = 25ma (external), en = low v do_vcc 200 mv
NCP81233 www.onsemi.com 10 table 3. electrical characteristics (continued) (v in = 12 v, typical values are referenced to t a = t j = 25 c, min and max values are referenced to t a = t j = ?40 c to 100 c. unless other noted.) characteristics units max typ min symbol test conditions vcc3v regulator output voltage ivcc3v = 5 ma (external), en = low v 3v3 3.1 3.3 3.5 v load regulation ivcc3v = 0.5 ma to 10 ma (external), en = low ?3.0 3.0 % supply current vin quiescent current en high, 1?phase only en high, 6?phase i qvin ? ? 11 17 20 28 ma ma vin shutdown current en low i sdvin ? 5 9 ma vref vref output voltage ivref = 500 a v vref 594 600 606 mv load regulation ivref = 0 ma to 2 ma ?1.0 1.0 % refin maximum refin voltage (note 7) 1.53 v refin bias current v refin = 1.0 v i refin ?100 100 na system voltag accuracy system voltage accuracy 0.5 v dac 1.52 v or 0.5 v refin 1.52 v ?40 c to 85 c ?7 7 mv ?40 cto 125 c ?10 10 0.25 v dac 0.495 v or 0.25 v refin 0.495 v ?40 c to 85 c ?8 8 ?40 c to 125 c ?12 12 differential voltage-sense amplifier vsp input voltage range (note 7) ?0.2 1.72 v vsn input voltage range (note 7) ?0.2 0.2 v dc gain vsp?vsn = 0 v to 1.52 v gain_dva 1.0 v/v ?3db gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd (note 7) bw_dva 10 mhz input bias current vsp = 1.72, vsn = ?0.2 v i vs ?400 400 na voltage error amplifier open-loop dc gain (note 7) gain ea 80 db unity gain bandwidth (note 7) gbw ea 20 mhz slew rate (note 7) sr comp 20 v/ s comp voltage swing i comp (source) = 2 ma v maxcomp 3.2 3.4 ? v i comp (sink) = 2 ma trbst is enabled v mincomp 0.3 v trbst is disabled ? 1.1 fb bias current v fb = 1.3v i fb ?400 400 na differential current-sense amplifier dc gain gain ca 6 v/v ?3db gain bandwidth (note 7) bw ca 10 mhz input common mode voltage range (note 7) ?0.2 vcc+0.1 v differential input voltage range (note 7) ?60 ? 60 mv input bias current isp, isn = 1.0 v i cs ?100 100 na
NCP81233 www.onsemi.com 11 table 3. electrical characteristics (continued) (v in = 12 v, typical values are referenced to t a = t j = 25 c, min and max values are referenced to t a = t j = ?40 c to 100 c. unless other noted.) characteristics units max typ min symbol test conditions current summing amplifier dc gain from (ispn ? isnn) to (cssum ? vbias) gain cssum ?2 v/v ?3db gain bandwidth cl = 10 pf to gnd, rl = 10 k to gnd (note 7) bw cssum 5 mhz cssum output offset all (ispn ? isnn) = 0 v (note 7) v oscssum ?7 0 7 mv maximum cssum output voltage i cssum (source) = 1 ma (note 7) 2.02 v minimum cssum output voltage i cssum (sink) = 1 ma (note 7) 0.56 v droop amplifier open-loop dc gain (note 7) gain da 80 db unity gain bandwidth (note 7) gbw da 10 mhz input offset voltage (note 7) v osda ?2.5 2.5 mv input bias current v dfb = 1.3v i dfb ?200 200 na maximum vdrp output voltage i vdrp (source) = 2 ma (note 7) 3.0 v minimum vdrp output voltage i vdrp (sink) = 2 ma (note 7) 1.0 v imon amplifier dc gain gain imon 10 v/v ?3db gain bandwidth (note 7) bw imon 2 mhz input offset voltage (note 7) v osimon ?2 2 mv output impedance (note 7) r imon 20 k imax sourcecurrent v imax = 1v 47.5 50 52.5 a i 2 c interface address address float short to gnd 2.7k 5.1k 8.2k 13k 20k 33k ? ? 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 ? ?
NCP81233 www.onsemi.com 12 table 3. electrical characteristics (continued) (v in = 12 v, typical values are referenced to t a = t j = 25 c, min and max values are referenced to t a = t j = ?40 c to 100 c. unless other noted.) characteristics test conditions symbol min typ max units vboot code vboot1 float short to gnd 2.7 k 5.1 k 8.2 k 13 k 20 k 33 k ? ? 000xxx 001xxx 010xxx 011xxx 100xxx 101xxx 110xxx 111xxx ? ? vboot2 float short to gnd 2.7 k 5.1 k 8.2 k 13 k 20 k 33 k ? ? xxx000 xxx001 xxx010 xxx011 xxx100 xxx101 xxx110 xxx111 ? ? source current i vbt 45 50 55 a switching frequency switching frequency 2.7 k 5.1 k float 8.2 k short to gnd 13 k 20 k 33 k f sw 180 270 360 450 540 720 900 1080 200 300 400 500 600 800 1000 1200 220 330 440 550 660 880 1100 1320 khz source current i fs 45 50 55 a system reset time system reset time measured from en to start of soft start. t rst 2.0 ms soft start soft?start slew rate float sssr 0.125 mv/us 33 k 0.25 20 k 0.5 13 k 1.0 8.2 k 2.0 5.1 k 4.0 2.7 k 8.0 short to gnd 16 source current i ss 45 50 55 a dvid dvid slew rate 000 sr 0.125 mv/us 001 0.25 010 0.5 011 1.0 100 2.0 101 4.0 110 8.0 111 16 i 2 c interface logic high input voltage v ih(sda, scl) 1.5 v
NCP81233 www.onsemi.com 13 table 3. electrical characteristics (continued) (v in = 12 v, typical values are referenced to t a = t j = 25 c, min and max values are referenced to t a = t j = ?40 c to 100 c. unless other noted.) characteristics units max typ min symbol test conditions i 2 c interface logic low input voltage v il(sda, scl) 0.7 v hysteresis 350 mv sda output low voltage i sda = ?4 ma v ol 0.3 v input current i ih ; i il ?1.0 1.0 a input capacitance (note 7) c scl, sda 5.0 pf clock frequency (note 7) f scl 400 khz scl falling edge to sda valid time (note 7) 1.0 s alert# low voltage i alert = ?4 ma v lalert 0. 3 v alert# leakage current alert# = 5 v i lkgalert 1 .0 a pgood pgood startup delay measured from end of soft start to pgood assertion (note 7) t d_pgood 100 s pgood shutdown delay measured from en to pgood de-assertion 25 0 ns pgood low voltage i pgood = ?4 ma v lpgood 0. 3 v pgood leakage current pgood = 5 v i lkgpgood 1 .0 a protections current limit threshold measured from ilimt to gnd isp?isn = 50 mv v octh 285 300 315 mv isp?isn = 2 0 mv 110 120 130 over current protection (ocp) debounce time (note 7) 8 cycles us under voltage threshold below dac vsp falling v uvth 250 300 350 mv under voltage protection (uvp) hysteresis v uvhys 25 mv under-voltage debounce time (note 7) 5 s shutdown time in hiccup mode uvp (note 7) ocp (note 7) otp (note 7) 30 40 20 ms absolute over voltage threshold during soft-start vsp-gnd 2.0 2.1 2.2 v absolute over voltage threshold hysteresis ?25 mv over voltage threshold above dac vsp rising v ovth 175 2 00 225 mv over voltage protection hysteresis vsp falling v ovhys ?25 mv over voltage debounce time vsp rising to gh low 1.0 us offset voltage of otp comparator vilmt = 200 mv v os_otp ?2 2 mv otp source current i otp 9 10 11 a otp debounce time (note 7) 140 ns thermal shutdown (tsd) threshold (note 7) t sd 140 150 c recovery temperature threshold (note 7) t rec 125 c thermal shutdown (tsd) debounce time (note 7) 120 ns
NCP81233 www.onsemi.com 14 table 3. electrical characteristics (continued) (v in = 12 v, typical values are referenced to t a = t j = 25 c, min and max values are referenced to t a = t j = ?40 c to 100 c. unless other noted.) characteristics units max typ min symbol test conditions enable en operation voltage range 0 3.5 v en on threshold v en_th 0.7 0.8 0.85 v hysteresis source current vcc5v is ok i en_hys 25 30 35 a drvon drvon operation voltage range 0 2.0 v drvon on threshold v drvon_th 0.75 0.8 0.85 v hysteresis source current vcc5v is ok i drvon_hys 25 30 35 a vb_rst# and psi high threshold v highrst 1.5 ? ? v low threshold v lowrst ? ? 0.7 v hysteresis v hysrst 350 mv input bias current external 1 k pull?up to 3.3 v i biasrst ? ? 1.0 a pwm modulation minimum on time (note 7) t on_min 50 ns minimum off time (note 7) t off_min 160 ns 0% duty cycle comp voltage when the pwm outputs remain lo (note 7) 1.3 v 100% duty cycle comp voltage when the pwm outputs remain hi, vin = 12.0 v (note 7) 2.5 v ramp feed forward voltage range (note 7) 4.5 20 v pwm output pwm output high voltage isourse = 0.5 ma v pwm_h v cc ?0.2 v pwm output low voltage isink = 0.5 ma v pwm_l 0.2 v rise and fall times cl (pcb) = 50 pf, measured between 10% & 90% of v cc (note 7) 10 ns leakage current in hi-z stage i lk_pwm ?1.0 1.0 a 7. guaranteed by design, not tested in production. table 4. resistor options for function programming resistance range (kw) resistor options (kw) min typ max 5% 1% 2.565 2.7 2.835 2.7 2.61 2.67 2.74 2.80 4.845 5.1 5.355 5.1 4.87 4.99 5.11 5.23 7.79 8.2 8.61 8.2 7.87 8.06 8.25 8.45 12.35 13 13.65 13 12.4 12.7 13 13.3 19 20 21 20 19.1 19.6 20 20.5 31.35 33 34.65 33 31.6 32.4 33.2 34
NCP81233 www.onsemi.com 15 table 5. vboot codes vboot1 vboot2 voltage(v) hex vboot1 vboot2 voltage(v) hex 0 0 0 0 0 0 0.6 00 1 0 0 0 0 0 0.92 20 0 0 0 0 0 1 0.61 01 1 0 0 0 0 1 0.93 21 0 0 0 0 1 0 0.62 02 1 0 0 0 1 0 0.94 22 0 0 0 0 1 1 0.63 03 1 0 0 0 1 1 0.95 23 0 0 0 1 0 0 0.64 04 1 0 0 1 0 0 0.96 24 0 0 0 1 0 1 0.65 05 1 0 0 1 0 1 0.97 25 0 0 0 1 1 0 0.66 06 1 0 0 1 1 0 0.98 26 0 0 0 1 1 1 0.67 07 1 0 0 1 1 1 0.99 27 0 0 1 0 0 0 0.68 08 1 0 1 0 0 0 1 28 0 0 1 0 0 1 0.69 09 1 0 1 0 0 1 1.01 29 0 0 1 0 1 0 0.7 0a 1 0 1 0 1 0 1.02 2a 0 0 1 0 1 1 0.71 0b 1 0 1 0 1 1 1.03 2b 0 0 1 1 0 0 0.72 0c 1 0 1 1 0 0 1.04 2c 0 0 1 1 0 1 0.73 0d 1 0 1 1 0 1 1.05 2d 0 0 1 1 1 0 0.74 0e 1 0 1 1 1 0 1.06 2e 0 0 1 1 1 1 0.75 0f 1 0 1 1 1 1 1.07 2f 0 1 0 0 0 0 0.76 10 1 1 0 0 0 0 1.08 30 0 1 0 0 0 1 0.77 11 1 1 0 0 0 1 1.09 31 0 1 0 0 1 0 0.78 12 1 1 0 0 1 0 1.1 32 0 1 0 0 1 1 0.79 13 1 1 0 0 1 1 1.11 33 0 1 0 1 0 0 0.8 14 1 1 0 1 0 0 1.12 34 0 1 0 1 0 1 0.81 15 1 1 0 1 0 1 1.13 35 0 1 0 1 1 0 0.82 16 1 1 0 1 1 0 1.14 36 0 1 0 1 1 1 0.83 17 1 1 0 1 1 1 1.15 37 0 1 1 0 0 0 0.84 18 1 1 1 0 0 0 1.16 38 0 1 1 0 0 1 0.85 19 1 1 1 0 0 1 1.17 39 0 1 1 0 1 0 0.86 1a 1 1 1 0 1 0 1.18 3a 0 1 1 0 1 1 0.87 1b 1 1 1 0 1 1 1.19 3b 0 1 1 1 0 0 0.88 1c 1 1 1 1 0 0 1.2 3c 0 1 1 1 0 1 0.89 1d 1 1 1 1 0 1 1.21 3d 0 1 1 1 1 0 0.9 1e 1 1 1 1 1 0 1.22 3e 0 1 1 1 1 1 0.91 1f 1 1 1 1 1 1 1.23 3f
NCP81233 www.onsemi.com 16 table 6. vid codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage (v) hex 0 0 0 0 0 0 0 0 off 00 0 0 0 0 0 0 0 1 0.25000 01 0 0 0 0 0 0 1 0 0.25500 02 0 0 0 0 0 0 1 1 0.26000 03 0 0 0 0 0 1 0 0 0.26500 04 0 0 0 0 0 1 0 1 0.27000 05 0 0 0 0 0 1 1 0 0.27500 06 0 0 0 0 0 1 1 1 0.28000 07 0 0 0 0 1 0 0 0 0.28500 08 0 0 0 0 1 0 0 1 0.29000 09 0 0 0 0 1 0 1 0 0.29500 0a 0 0 0 0 1 0 1 1 0.30000 0b 0 0 0 0 1 1 0 0 0.30500 0c 0 0 0 0 1 1 0 1 0.31000 0d 0 0 0 0 1 1 1 0 0.31500 0e 0 0 0 0 1 1 1 1 0.32000 0f 0 0 0 1 0 0 0 0 0.32500 10 0 0 0 1 0 0 0 1 0.33000 11 0 0 0 1 0 0 1 0 0.33500 12 0 0 0 1 0 0 1 1 0.34000 13 0 0 0 1 0 1 0 0 0.34500 14 0 0 0 1 0 1 0 1 0.35000 15 0 0 0 1 0 1 1 0 0.35500 16 0 0 0 1 0 1 1 1 0.36000 17 0 0 0 1 1 0 0 0 0.36500 18 0 0 0 1 1 0 0 1 0.37000 19 0 0 0 1 1 0 1 0 0.37500 1a 0 0 0 1 1 0 1 1 0.38000 1b 0 0 0 1 1 1 0 0 0.38500 1c 0 0 0 1 1 1 0 1 0.39000 1d 0 0 0 1 1 1 1 0 0.39500 1e 0 0 0 1 1 1 1 1 0.40000 1f 0 0 1 0 0 0 0 0 0.40500 20 0 0 1 0 0 0 0 1 0.41000 21
NCP81233 www.onsemi.com 17 table 6. vid codes (continued) vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 0 1 0 0 0 1 0 0.41500 22 0 0 1 0 0 0 1 1 0.42000 23 0 0 1 0 0 1 0 0 0.42500 24 0 0 1 0 0 1 0 1 0.43000 25 0 0 1 0 0 1 1 0 0.43500 26 0 0 1 0 0 1 1 1 0.44000 27 0 0 1 0 1 0 0 0 0.44500 28 0 0 1 0 1 0 0 1 0.45000 29 0 0 1 0 1 0 1 0 0.45500 2a 0 0 1 0 1 0 1 1 0.46000 2b 0 0 1 0 1 1 0 0 0.46500 2c 0 0 1 0 1 1 0 1 0.47000 2d 0 0 1 0 1 1 1 0 0.47500 2e 0 0 1 0 1 1 1 1 0.48000 2f 0 0 1 1 0 0 0 0 0.48500 30 0 0 1 1 0 0 0 1 0.49000 31 0 0 1 1 0 0 1 0 0.49500 32 0 0 1 1 0 0 1 1 0.50000 33 0 0 1 1 0 1 0 0 0.50500 34 0 0 1 1 0 1 0 1 0.51000 35 0 0 1 1 0 1 1 0 0.51500 36 0 0 1 1 0 1 1 1 0.52000 37 0 0 1 1 1 0 0 0 0.52500 38 0 0 1 1 1 0 0 1 0.53000 39 0 0 1 1 1 0 1 0 0.53500 3a 0 0 1 1 1 0 1 1 0.54000 3b 0 0 1 1 1 1 0 0 0.54500 3c 0 0 1 1 1 1 0 1 0.55000 3d 0 0 1 1 1 1 1 0 0.55500 3e 0 0 1 1 1 1 1 1 0.56000 3f 0 1 0 0 0 0 0 0 0.56500 40 0 1 0 0 0 0 0 1 0.57000 41 0 1 0 0 0 0 1 0 0.57500 42 0 1 0 0 0 0 1 1 0.58000 43
NCP81233 www.onsemi.com 18 table 6. vid codes (continued) vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 1 0 0 0 1 0 0 0.58500 44 0 1 0 0 0 1 0 1 0.59000 45 0 1 0 0 0 1 1 0 0.59500 46 0 1 0 0 0 1 1 1 0.60000 47 0 1 0 0 1 0 0 0 0.60500 48 0 1 0 0 1 0 0 1 0.61000 49 0 1 0 0 1 0 1 0 0.61500 4a 0 1 0 0 1 0 1 1 0.62000 4b 0 1 0 0 1 1 0 0 0.62500 4c 0 1 0 0 1 1 0 1 0.63000 4d 0 1 0 0 1 1 1 0 0.63500 4e 0 1 0 0 1 1 1 1 0.64000 4f 0 1 0 1 0 0 0 0 0.64500 50 0 1 0 1 0 0 0 1 0.65000 51 0 1 0 1 0 0 1 0 0.65500 52 0 1 0 1 0 0 1 1 0.66000 53 0 1 0 1 0 1 0 0 0.66500 54 0 1 0 1 0 1 0 1 0.67000 55 0 1 0 1 0 1 1 0 0.67500 56 0 1 0 1 0 1 1 1 0.68000 57 0 1 0 1 1 0 0 0 0.68500 58 0 1 0 1 1 0 0 1 0.69000 59 0 1 0 1 1 0 1 0 0.69500 5a 0 1 0 1 1 0 1 1 0.70000 5b 0 1 0 1 1 1 0 0 0.70500 5c 0 1 0 1 1 1 0 1 0.71000 5d 0 1 0 1 1 1 1 0 0.71500 5e 0 1 0 1 1 1 1 1 0.72000 5f 0 1 1 0 0 0 0 0 0.72500 60 0 1 1 0 0 0 0 1 0.73000 61 0 1 1 0 0 0 1 0 0.73500 62 0 1 1 0 0 0 1 1 0.74000 63 0 1 1 0 0 1 0 0 0.74500 64 0 1 1 0 0 1 0 1 0.75000 65
NCP81233 www.onsemi.com 19 table 6. vid codes (continued) vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 1 1 0 0 1 1 0 0.75500 66 0 1 1 0 0 1 1 1 0.76000 67 0 1 1 0 1 0 0 0 0.76500 68 0 1 1 0 1 0 0 1 0.77000 69 0 1 1 0 1 0 1 0 0.77500 6a 0 1 1 0 1 0 1 1 0.78000 6b 0 1 1 0 1 1 0 0 0.78500 6c 0 1 1 0 1 1 0 1 0.79000 6d 0 1 1 0 1 1 1 0 0.79500 6e 0 1 1 0 1 1 1 1 0.80000 6f 0 1 1 1 0 0 0 0 0.80500 70 0 1 1 1 0 0 0 1 0.81000 71 0 1 1 1 0 0 1 0 0.81500 72 0 1 1 1 0 0 1 1 0.82000 73 0 1 1 1 0 1 0 0 0.82500 74 0 1 1 1 0 1 0 1 0.83000 75 0 1 1 1 0 1 1 0 0.83500 76 0 1 1 1 0 1 1 1 0.84000 77 0 1 1 1 1 0 0 0 0.84500 78 0 1 1 1 1 0 0 1 0.85000 79 0 1 1 1 1 0 1 0 0.85500 7a 0 1 1 1 1 0 1 1 0.86000 7b 0 1 1 1 1 1 0 0 0.86500 7c 0 1 1 1 1 1 0 1 0.87000 7d 0 1 1 1 1 1 1 0 0.87500 7e 0 1 1 1 1 1 1 1 0.88000 7f 1 0 0 0 0 0 0 0 0.88500 80 1 0 0 0 0 0 0 1 0.89000 81 1 0 0 0 0 0 1 0 0.89500 82 1 0 0 0 0 0 1 1 0.90000 83 1 0 0 0 0 1 0 0 0.90500 84 1 0 0 0 0 1 0 1 0.91000 85 1 0 0 0 0 1 1 0 0.91500 86 1 0 0 0 0 1 1 1 0.92000 87
NCP81233 www.onsemi.com 20 table 6. vid codes (continued) vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 0 0 0 1 0 0 0 0.92500 88 1 0 0 0 1 0 0 1 0.93000 89 1 0 0 0 1 0 1 0 0.93500 8a 1 0 0 0 1 0 1 1 0.94000 8b 1 0 0 0 1 1 0 0 0.94500 8c 1 0 0 0 1 1 0 1 0.95000 8d 1 0 0 0 1 1 1 0 0.95500 8e 1 0 0 0 1 1 1 1 0.96000 8f 1 0 0 1 0 0 0 0 0.96500 90 1 0 0 1 0 0 0 1 0.97000 91 1 0 0 1 0 0 1 0 0.97500 92 1 0 0 1 0 0 1 1 0.98000 93 1 0 0 1 0 1 0 0 0.98500 94 1 0 0 1 0 1 0 1 0.99000 95 1 0 0 1 0 1 1 0 0.99500 96 1 0 0 1 0 1 1 1 1.00000 97 1 0 0 1 1 0 0 0 1.00500 98 1 0 0 1 1 0 0 1 1.01000 99 1 0 0 1 1 0 1 0 1.01500 9a 1 0 0 1 1 0 1 1 1.02000 9b 1 0 0 1 1 1 0 0 1.02500 9c 1 0 0 1 1 1 0 1 1.03000 9d 1 0 0 1 1 1 1 0 1.03500 9e 1 0 0 1 1 1 1 1 1.04000 9f 1 0 1 0 0 0 0 0 1.04500 a0 1 0 1 0 0 0 0 1 1.05000 a1 1 0 1 0 0 0 1 0 1.05500 a2 1 0 1 0 0 0 1 1 1.06000 a3 1 0 1 0 0 1 0 0 1.06500 a4 1 0 1 0 0 1 0 1 1.07000 a5 1 0 1 0 0 1 1 0 1.07500 a6 1 0 1 0 0 1 1 1 1.08000 a7 1 0 1 0 1 0 0 0 1.08500 a8 1 0 1 0 1 0 0 1 1.09000 a9
NCP81233 www.onsemi.com 21 table 6. vid codes (continued) vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 0 1 0 1 0 1 0 1.09500 aa 1 0 1 0 1 0 1 1 1.10000 ab 1 0 1 0 1 1 0 0 1.10500 ac 1 0 1 0 1 1 0 1 1.11000 ad 1 0 1 0 1 1 1 0 1.11500 ae 1 0 1 0 1 1 1 1 1.12000 af 1 0 1 1 0 0 0 0 1.12500 b0 1 0 1 1 0 0 0 1 1.13000 b1 1 0 1 1 0 0 1 0 1.13500 b2 1 0 1 1 0 0 1 1 1.14000 b3 1 0 1 1 0 1 0 0 1.14500 b4 1 0 1 1 0 1 0 1 1.15000 b5 1 0 1 1 0 1 1 0 1.15500 b6 1 0 1 1 0 1 1 1 1.16000 b7 1 0 1 1 1 0 0 0 1.16500 b8 1 0 1 1 1 0 0 1 1.17000 b9 1 0 1 1 1 0 1 0 1.17500 ba 1 0 1 1 1 0 1 1 1.18000 bb 1 0 1 1 1 1 0 0 1.18500 bc 1 0 1 1 1 1 0 1 1.19000 bd 1 0 1 1 1 1 1 0 1.19500 be 1 0 1 1 1 1 1 1 1.20000 bf 1 1 0 0 0 0 0 0 1.20500 c0 1 1 0 0 0 0 0 1 1.21000 c1 1 1 0 0 0 0 1 0 1.21500 c2 1 1 0 0 0 0 1 1 1.22000 c3 1 1 0 0 0 1 0 0 1.22500 c4 1 1 0 0 0 1 0 1 1.23000 c5 1 1 0 0 0 1 1 0 1.23500 c6 1 1 0 0 0 1 1 1 1.24000 c7 1 1 0 0 1 0 0 0 1.24500 c8 1 1 0 0 1 0 0 1 1.25000 c9 1 1 0 0 1 0 1 0 1.25500 ca 1 1 0 0 1 0 1 1 1.26000 cb
NCP81233 www.onsemi.com 22 table 6. vid codes (continued) vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 1 0 0 1 1 0 0 1.26500 cc 1 1 0 0 1 1 0 1 1.27000 cd 1 1 0 0 1 1 1 0 1.27500 ce 1 1 0 0 1 1 1 1 1.28000 cf 1 1 0 1 0 0 0 0 1.28500 d0 1 1 0 1 0 0 0 1 1.29000 d1 1 1 0 1 0 0 1 0 1.29500 d2 1 1 0 1 0 0 1 1 1.30000 d3 1 1 0 1 0 1 0 0 1.30500 d4 1 1 0 1 0 1 0 1 1.31000 d5 1 1 0 1 0 1 1 0 1.31500 d6 1 1 0 1 0 1 1 1 1.32000 d7 1 1 0 1 1 0 0 0 1.32500 d8 1 1 0 1 1 0 0 1 1.33000 d9 1 1 0 1 1 0 1 0 1.33500 da 1 1 0 1 1 0 1 1 1.34000 db 1 1 0 1 1 1 0 0 1.34500 dc 1 1 0 1 1 1 0 1 1.35000 dd 1 1 0 1 1 1 1 0 1.35500 de 1 1 0 1 1 1 1 1 1.36000 df 1 1 1 0 0 0 0 0 1.36500 e0 1 1 1 0 0 0 0 1 1.37000 e1 1 1 1 0 0 0 1 0 1.37500 e2 1 1 1 0 0 0 1 1 1.38000 e3 1 1 1 0 0 1 0 0 1.38500 e4 1 1 1 0 0 1 0 1 1.39000 e5 1 1 1 0 0 1 1 0 1.39500 e6 1 1 1 0 0 1 1 1 1.40000 e7 1 1 1 0 1 0 0 0 1.40500 e8 1 1 1 0 1 0 0 1 1.41000 e9 1 1 1 0 1 0 1 0 1.41500 ea 1 1 1 0 1 0 1 1 1.42000 eb 1 1 1 0 1 1 0 0 1.42500 ec 1 1 1 0 1 1 0 1 1.43000 ed
NCP81233 www.onsemi.com 23 table 6. vid codes (continued) vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 1 1 0 1 1 1 0 1.43500 ee 1 1 1 0 1 1 1 1 1.44000 ef 1 1 1 1 0 0 0 0 1.44500 f0 1 1 1 1 0 0 0 1 1.45000 f1 1 1 1 1 0 0 1 0 1.45500 f2 1 1 1 1 0 0 1 1 1.46000 f3 1 1 1 1 0 1 0 0 1.46500 f4 1 1 1 1 0 1 0 1 1.47000 f5 1 1 1 1 0 1 1 0 1.47500 f6 1 1 1 1 0 1 1 1 1.48000 f7 1 1 1 1 1 0 0 0 1.48500 f8 1 1 1 1 1 0 0 1 1.49000 f9 1 1 1 1 1 0 1 0 1.49500 fa 1 1 1 1 1 0 1 1 1.50000 fb 1 1 1 1 1 1 0 0 1.50500 fc 1 1 1 1 1 1 0 1 1.51000 fd 1 1 1 1 1 1 1 0 1.51500 fe 1 1 1 1 1 1 1 1 1.52000 ff
NCP81233 www.onsemi.com 24 table 7. standard command codes (part 1) command code r/w default description # bytes comment 0x01 r/w 0x80 operation 1 operation command turns the device on or off in conjunction with en signal. bit default r/w comment 7 1 r/w 0: immediate off; 1: on (slew rate set by soft-start) default 6 0 r (reserved for future use.) 5:2 0000 r margin operation. (reserved for future use.) 1:0 00 r (reserved for future use.) 0x02 r/w 0x17 on_off_config 1 configures how the controller is turned on and off. bit default r/w comment 7:5 000 r (reserved for future use.) 4 1 r switching starts when commanded by the en pin and the operation command, as set in bits 3:0 3 0 r/w 0: unit ignores operation commands over the i 2 c interface 1: unit responds to operation command, power up may also depend upon en input, as described in bit 2 2 1 r 0: unit ignores en pin 1: unit responds en pin, power up may also depend upon the operation register, as described for bit 3 1 1 r en pin polarity 0 = active low 1 = active high 0 1 r 1: when the controller is disabled it will immediately turn off (as set in the operation command) 0x03 w na clear_faults 0 writing any value to this command code will clear all status bits immediately. the alert# is deasserted on this command. if the fault is still present the fault bit shall immediately be asserted again. this command is write only. there is no data byte for this command. 0x19 r 0xb0 capability 1 this command allows the host to get some information on the i 2 c device. bit default r/w comment 7 1 r pec (packet error checking is supported) 6:5 01 r supported maximum bus speed is 400 khz 4 1 r NCP81233 has an alert# pin and alert response address (ara) protocol is supported 3:0 0000 r (reserved for future use.)
NCP81233 www.onsemi.com 25 table 7. standard command codes (part 1) (continued) command code comment # bytes description default r/w 0x20 r 0x20 vout_mode 1 the NCP81233 supports vid mode for programming the output voltage. 0x21 r/w 0x0000 vout_command 2 sets the output voltage using vid in low byte. 0x24 r/w 0x00ff vout_max 2 sets maximum output voltage (vid data format). (reserved for future use.) 0xa4 r/w 0x0000 vout_min 2 sets minimum output voltage (vid data format). (reserved for future use.) 0x60 r/w 0x0000 ton_delay 2 sets the delay time, in ms, from the end of system reset until the output voltage starts to rise. the lowest 4 bits of the high byte is valid, i.e. 0x0000 = 0ms 0x0100 = 1ms 0x0200 = 2ms 0x0f00 = 15ms 0x78 r 0x00 status byte 1 bit name description 7 busy a fault was declared because the NCP81233 was busy and unable to respond 6 off this bit is set whenever the NCP81233 is not switching 5 vout_ov this bit gets set whenever the NCP81233 goes into ovp (abs ovp and/or normal ovp) mode. 4 iout_oc this bit gets set whenever the NCP81233 turns off due to an over current event. 3 vin_uv not supported. 2 ot this bit gets set whenever the NCP81233 turns off due to an over temperature event. 1 cml this bit gets set whenever a communications or logic fault has occurred. 0 none of the above a fault has occurred which is not one of the above.
NCP81233 www.onsemi.com 26 table 7. standard command codes (part 1) (continued) command code comment # bytes description default r/w 0x79 r 0x0000 status word 2 byte bit name description low 7 busy a fault was declared because the NCP81233 was busy and unable to respond. 6 off this bit is set whenever the NCP81233 is not switching. 5 vout _ov this bit gets set whenever the NCP81233 goes into ovp mode. 4 iout_ oc this bit gets set whenever the NCP81233 turns off due to an over current event. 3 vin_ uv not supported. 2 ot this bit gets set whenever the NCP81233 turns off due to an over temperature event. 1 cml this bit gets set whenever a communications or logic fault has occurred. 0 none of the above a fault has occurred which is not one of the above. high 7 vout this bit gets set whenever the measured output voltage goes outside its power good limits or an ovp/uvp event has taken place. i.e. any bit in status vout is set. 6 iout/ pout this bit gets set whenever the measured output current or power exceeds its warning limit or goes into ocp. i.e. any bit in status iout is set. 5 (reserved for future use.) 4 (reserved for future use.) 3 power good # the vdd_pwrgd signal is deasserted. same as powergood in general status. 2 (reserved for future use.)
NCP81233 www.onsemi.com 27 table 8. standard command codes (part 2) command code r/w default description # bytes comment 0x7a r 0x00 status vout 1 bit name description 7 vout_over voltage fault this bit gets set whenever an ovp event takes place. 6 vout_over voltage warning this bit gets set whenever the measured output voltage goes above its power-good limit. (reserved for future use.) 5 vout_ under voltage warning this bit gets set whenever the measured output voltage goes below its power good limit. (reserved for future use.) 4 vout_unde rvoltage fault this bit gets set whenever an uvp event takes place. 3 (reserved for future use.) 2 (reserved for future use.) 1 (reserved for future use.) 0 (reserved for future use.) 0x7b r 0x00 status iout 1 bit name description 7 iout_over current fault this bit gets set if the NCP81233 turns off due to an ocp event 6 (reserved for future use.) 5 iout_over current warning this bit gets set if i out exceeds its programmed high warning limit. (reserved for future use.) 4 (reserved for future use.) 3 (reserved for future use.) 2 (reserved for future use.) 1 (reserved for future use.) 0 (reserved for future use.) 0x7e r 0x00 status cml 1 bit name description 7 invalid command invalid or unsupported command is received. (reserved for future use.) 6 invalid data invalid or unsupported data is received. (reserved for future use.) 5 pec_fault pec failed. (reserved for future use.) 4 (reserved for future use.) 3 (reserved for future use.) 2 (reserved for future use.) 1 others a communication fault other than the ones listed has occurred. (reserved for future use.) 0 (reserved for future use.)
NCP81233 www.onsemi.com 28 table 8. standard command codes (part 2) (continued) command code comment # bytes description default r/w 0x80 r 0x00 status_ alert 1 bit name description 7 (reserved for future use.) 6 (reserved for future use.) 5 (reserved for future use.) 4 (reserved for future use.) 3 (reserved for future use.) 2 v mon warn gets asserted when v mon exceeds it programmed warn limits. (reserved for future use.) 1 v mon fault gets asserted when v mon exceeds it programmed fault limits. (reserved for future use.) 0 (reserved for future use.) 0x8b r 0x0000 read_vout 2 readback output voltage. voltage is read back in vid mode. 0x8c r 0x0000 read_iout 2 readback output current. current is read back in linear mode with unit of amp. 0x99 r 0x1a mfr_id 1 0x9a r 0x1233 mfr_ model 2 0x9b r 0x00 mfr_ revision 1 table 9. manufacturer specific command codes command code r/w default description # bytes comment 0xd0 r/w 0x00 lock/reset 1 bit name description 1 reset resets all registers to their por value. has no effect if lock bit is set. 0 lock logic 1 locks all limit values to their current settings. once this bit is set, all lockable registers become read*only and cannot be modified until the NCP81233 is powered down and powered up again. this prevents rogue programs such as viruses from modifying critical system limit settings. (lockable).
NCP81233 www.onsemi.com 29 table 9. manufacturer specific command codes (continued) command code comment # bytes description default r/w 0xd6 r/w 0x00 vout slew rate 1 bit name description 7:5 dvid slew rate dvid slew rate is automatically set to the same value as soft-start slew rate after each startup, which is programmed by ss pin. after that, it can be adjusted by i 2 c interface. 000 = 0.125mv/us 001 = 0.25mv/us 010 = 0.5mv/us 011 = 1mv/us 100 = 2mv/us 101 = 4mv/us 110 = 8mv/us 111= 16mv/us 4:2 (reserved for future use.) 1 (reserved for future use.) 0 (reserved for future use.) 0xdd r 0x0000 read_imax 2 maximum load current value, which is set at imax pin. the unit is amp. 0xf9 r/w 0x00 mask alert 1 bit name description 7 mask vout masks any alert caused by bits in status vout register. 6 mask iout masks any alert caused by bits in status iout register. 5 mask ov fault masks any alert caused by ovp (abs ovp and normal ovp). 4 mask uv fault masks any alert caused by uvp. 3 mask oc fault masks any alert caused by ocp. 2 mask ot fault masks any alert caused by otp. 1 mask cml masks any alert caused by bits in status cml register. 0 vmon masks any alert caused by vmon exceeding its high or low limit. (reserved for future use.)
NCP81233 www.onsemi.com 30 detailed description general the NCP81233, a multi-phase synchronous buck controller with an i 2 c interface, provides power management solutions for applications supported by drmos. it supports 1-, 2-, 3-, 4-, or 6-phase operation and provides differential voltage and current sense, flexible programming, and comprehensive protections. operation modes the number of operational phases is programmed at config pin as shown in table 10. all used phases are paralleled together in output of power stage with a common voltage-sense feedback. all input pins of current senses in unused phases can be left float. table 10. config configuration config r config phase number phase number float pwm1+pwm2+pwm3+pwm4+pwm5+pwm6 6 short to gnd pwm1+pwm2+pwm3+pwm4 4 33k pwm1+pwm2+pwm3 3 13k pwm1+pwm2 2 5.1k pwm1 1 other control functions can be programmed at mode1 pin and mode2 pin as shown in table 11 and table 12. table 11. mode 1 configuration mode1 r mode1 ovp & uvp ovp option ocp, uvp, otp float enabled recoverable hiccup 33 k latch off 20 k latch off hiccup 13 k latch off 8.2 k disabled disabled latch off 5.1 k 2.7 k hiccup short to gnd table 12. mode 2 configuration mode2 r mode2 regulation reference pin 27 function otp option float vboot/vid vb_rst# otp1 33 k otp2 20 k psi otp1 13 k otp2 8.2 k refin psi otp2 5.1 k 2.7 k otp1 short to gnd in applications with an external analog reference input, the device needs to be programmed at mode2 pin to select refin as the regulation reference. once refin is selected as the regulation reference, the command vout_command through i 2 c interface won?t be proceeded and the readback result of the command read_vout is ffh.
NCP81233 www.onsemi.com 31 power sequence and soft start the NCP81233 has a soft start function and the soft start slew rate is externally programmed at ss pins. the output starts to ramp up following a system reset period trst and a programmable delay time t on_dly after the device is enabled and vcc is ok. the system reset time is about 2 ms. the value of t on_dly can be programmed by ton_delay command and the default value is zero. when the device is disabled or uvlo happens, the device shuts down immediately and all the pwm turn to tri-state. figure 6. timing diagrams of power up sequence en vcc5v vout t rst t ss pgood t d_pgood drvon pwm tri?state t en vcc5v vout t ss pgood t d_pgood v ccok pwm tri?state drvon v drvon_ok t rst (1) vcc5v and drvon ready before en (2) vcc5v and drvon ready after en on_dlt t on_dlt figure 7. timing diagram of power down sequence en vcc5v vout pgood drvon pwm figure 8. timing diagram of drvon uvlo en vcc5v vout pgood d rvon pwm t ss t d_pgoo d tri?state v drvon_f v drvon_ok t rst t on_dlt
NCP81233 www.onsemi.com 32 figure 9. enable, drvon and uvlo en_int i en_hys v en_th vcc3v uvlo vcc3v ok i drvon_hys v drvon_th vcc3v drvon en vcc5v uvlo vcc5v ok vcc5v 0x02<3> 0x01<7> the device is able to start up smoothly under an output pre-biased condition without discharging the output before ramping up. in applications with external analog refin, soft start completes when the internal dac reaches refin.
NCP81233 www.onsemi.com 33 enable and input uvlo the NCP81233 is enabled when the voltage at en pin is higher than an internal threshold v en_th = 0.8 v. a hysteresis can be programmed by an external resistor r en connected to en pin as shown in figure 10. the high threshold v en_h in enable signal is v en_h v en_th (eq. 1) figure 10. enable and hysteresis programming en_int enable r en v en_th v en_h v en_l i en_hys the low threshold v en_l in enable signal is: v en_l v en_th v en_hys (eq. 2) the hysteresis v en_hys is: v en_hys i en_hys r en (eq. 3) a uvlo function for input power supply can be implemented at en pin. as shown in figure 11, the uvlo threshold can be programmed by two external resistors. the high threshold v in_h in vin signal is: v in_h r en1 r en2 1 v en_th (eq. 4) the low threshold v in_l in vin signal is: v in_l v in_h v in_hys (eq. 5) the hysteresis v in_hys is: v in_hys i en_hys r en1 (eq. 6) figure 11. enable and input supply uvlo circuit en_int vin r en1 r en2 v en_th v in_h v in_l i en_hys to avoid undefined operation, en pin should not be left float in applications. drvon and drmos power monitor the NCP81233 provides comprehensive power up sequence control including a drmos power monitor to ensure proper operation of drmos during power up and down. similar to the uvlo function for input power supply implemented at en pin, as shown in figure 12, the uvlo threshold for drmos power can be programmed by two external resistors. the high threshold v drv_h in the driver supply of drmos can be programmed as: v drv_h r drv1 r drv2 1 v drvon_th (eq. 7) the low threshold v drv_l in the driver supply of drmos is: v drv_l v drv_h v drv_hys (eq. 8) the hysteresis v drv_hys is v drv_hys i drvon_hys r drv1 (eq. 9)
NCP81233 www.onsemi.com 34 figure 12. drvon and drmos supply uvlo circuit en_int drv on i drvon_hys v drvon_th v drv r drv1 v drv_h v drv_l r drv2 drvon pwm 5 v vswh cgnd pgnd ncp5339 vdrv pwm vin vswh cgnd pgnd ncp5339 vdrv pwm vin vswh cgnd pgnd ncp5339 vdrv vin to avoid undefined operation, drvon pin should not be left float in applications. in an application using phase doublers, drvon pin may be used to monitor a common power supply shared by both phase doublers and drmoss. vboot restore on condition that vboot restore (vb_rst#) function is selected for pin 27 by function programming at mode2 pin, the NCP81233 has a capability to restore to boot voltage once pin 27 is pulled low for more than 4ms after pgood is asserted. the output voltage slew rate has the same value as soft start. power saving interface (psi) on condition that psi function is selected for pin 27 by function programming at mode2 pin, the NCP81233 has 2 power operation modes responding to psi levels as shown in table 13. the operation modes can be changed on the fly after pgood is asserted. in ps0 mode, the operating phases are determined by the configuration programming at config pin. in ps1 mode, only pwm1 is active while high impedance in other pwm outputs. table 13. power saving interface (psi) configurations psi level power mode phase configuration high ps0 multi-phase, fccm low ps1 1-phase, fccm pwm output to be able to operate with diverse drmoss and phase doublers, the n cp81233 has 6 tri-level pwm outputs which may be connected to pwm inputs of these receivers. as shown in figure 13, an internal transistor s h in the NCP81233 pulls a pwm pin up to pvcc when outputs a high level and another internal transistor s l pulls the pwm pin down to gnd when outputs a low level. when there is a need to have a mid-level at the pwm input of a drmos or a phase doubler during power sequence or fault modes, both s h and s l are turned off and therefore the pwm output of the NCP81233 is left float. to well adapt the mid-level window of the receiver?s pwm input, an external resistor divider composed of r h and r l is required in the connection between the NCP81233 and the receiver if no internal resistor divider in the receiver. moreover, reduced input impedance by an external resistor also speeds up entering mid-level from either high level or low level for a receiver having an internal resistor divider.
NCP81233 www.onsemi.com 35 figure 13. pwm connections to drmos and phase doubler pwm 145k 129k 3.4v r h r l pwm NCP81233 ncp5339 r s s h pvcc s l 0 10k 10k vcin pwm_in vcc r h r l pwm NCP81233 ncp81162 r s s h pvcc s l 0 15k 10k ( a ) connected to drmos ( b ) connected to phase doubler the NCP81233 works with most of drmoss having either 5 v or 3.3 v pwm input logic. however, for some 3.3 v-logic drmoss having a low maximum voltage rating of pwm pins which is less than the pvcc level of the NCP81233, an additional resistor r s may be inserted into the interconnection, as shown in figure 13, to reduce the high voltage level. note the insertion of r s also raises the low voltage level at the pwm input of the receiver, so the resistance of r s needs to be properly designed to meet the receiver?s specification on both high level and low level. output voltage sensing and regulation figure 14. output voltage sensing and regulation vsp vsn diffout v dac or v refin fb comp r fb1 v bias r vs2 r vs1 r vs3 vout the NCP81233 has a dif ferential voltage-sense amplifier. as shown in figure 14, the remote voltage sensing points are connected to input pins vsp and vsn of the differential voltage-sense amplifier via a resistor network composed by r vs1 , r vs2 , and r vs3 . for applications with v out 1.52 v, r vs1 = r vs3 = 0 or 100 and r vs2 is left open. in steady-state, v out = v dac . for applications with v out > 1.52 v, the output voltage needs to be divided down by the resistor network to have vsp-vsn be within dac range. usually r vs3 is set to 0 or 100 . given a preset value of r vs2 , then the value of r vs1 can be obtained by r vs1 v out v dac r vs2 v dac r vs3 (eq. 10) a small offset voltage can also be added in output if needed. as sh own in figure 15, a resistor divider composed by r 1 and r 2 is connected from vref to the negative remote sense point and feeds an offset voltage into vsn pin. by doing this way, the output voltage is: v out v dac v ref r 1 r 1 r 2 (eq. 11)
NCP81233 www.onsemi.com 36 figure 15. adding offset voltage in output vsn vref NCP81233 vsp r1 r2 vout + vout ? imax the i 2 c interface conveys the platform imax value to the master by command read_imax. a resistor r imax from the imax pin to ground programs this register at the time the part is enabled. a 50 a current is sourced out this pin to generate a voltage across the programming resistor. the maximum voltage at imax pin is 2 v and the maximum value in the imax register 0xddh is 00ffh which is 255 in decimal. for applications with a maximum load i out_max equal to or less than 255 a, the value imax ddh of the register is 1 a per lsb and directly represents i out_max . for applications with a maximum load iout_max greater than 255 a, the resistor should be equal or higher than 39.8 k, which results in 00ffh in the imax register. i out_max if i out_max 255 a (eq. 12) 255 if i out_max 255 a imax ddh i out_max 6.4x10 3 if i out_max 255 a (eq. 13) 39.8 k or higher, if i out_max 255 a r imax figure 16. imax, imon, and load line fb comp diffout vdrp vdfb cssum r dfb r x1 r drp r fb1 rntc r x3 r x2 10 isp1?isn1 vbias ?2 imon vbias imax r x r imax c imon ispn?isnn imon the voltage of the imon pin is monitored by the internal a/d converter and should be scaled with external resistors, r x and r dfb , surround the droop amplifier such that the maximum load current i out_max in an application generates a 2 v signal at imon pin. therefore, the gain-up ratio r x /r dfb can be designed as below. r x r dfb 1 10 1 n n 1 v ispn v isnn (eq. 14) r x can be replaced by a resistor network with a ntc resistor to compensate temperature effect on the dcr of inductor. the filtered voltage at imon pin is
NCP81233 www.onsemi.com 37 v imon 20 r x r dfb n n 1 v ispn v isnn (eq. 15) the i 2 c interface conveys the iout value to the master by command read_iout . the maximum value in the iout register 0x8ch is 00ffh which is 255 in decimal. for applications with a maximum load equal to or less than 255a, the value iout 8ch in the register is 1 a per lsb which directly represents the output load current value in amperes. for applications with a maximum load greater than 255 a, the real output current value can be obtained from the reading iout 8ch in the register with a coefficient of i out_max /255. iout 8ch if i out_max 255 a (eq. 16) i out iout 8ch 255 i out_max if i out_max 255 a load line programming in applications with a need of programmable load line, the output of the droop amplifier needs to be connected to fb pin by an external resistor rdrp as shown in figure 16. droop voltage vdroop in diffout output can be obtained by: v droop 2 r fb1 r drp r x r dfb n n 1 v ispn v isnn (eq. 17) dc load line ll in output is: l l 2 r fb1 r drp r x r dfb r vs1 r vs2 r vs3 r vs2 dcr (eq. 18 ) over voltage protection (ovp) by means of the configuration at mode1 pin as shown in table 11, the users can choose either recoverable ovp or latch-off ovp. recoverable ovp during normal operation the output voltage is monitored at the dif ferential inputs vsp and vsn. if vsp-vsn voltage exceeds the dac+v ovth (or refin+v ovth ) for more than 1us, over voltage protection ovp is triggered and pgood is pulled low. in the meanwhile, all the high-side mosfets are turned off and all the low-side mosfets are turned on. the over voltage protection can be cleared once vsp-vsn voltage drops 25mv lower than dac+v ovth (or refin+v ovth ), and then the system comes back to normal operation. during soft-start, the ovp threshold is set to 2.1v before pgood is asserted, but it changes to dac+v ovth (or refin+v ovth ) after ovp is triggered. latch-off ovp figure 17. function of latch-off over voltage protection ( a ) normal operation mode ( b ) during start up during normal operation the output voltage is monitored at the dif ferential inputs vsp and vsn. if vsp-vsn voltage exceeds the dac+v ovth (or refin+v ovth ) for more than 1us, over voltage protection ovp is triggered and pgood is pulled low. in the meanwhile, all the high-side mosfets are latched off and all the low-side mosfets are turned on. after the ovp trips, the dac ramps slowly down to zero, having a slew rate of ?0.5 mv/us to avoid a negative output voltage spike during shutdown. all the low-side mosfets toggle between on and off as the output voltage follows the dac+v ovth (or refin+v ovth ) down with a hysteresis of 25 mv. when the dac gets to zero, all the high-side mosfets will be held off and all the low-side mosfets will remain on. during soft-start, the ovp threshold is set to 2.1 v, and it changes to dac+v ovth (or refin+v ovth ) after dac starts to ramp down. to restart the device after latch-off ovp, the system needs to have either vcc5v or en toggled state.
NCP81233 www.onsemi.com 38 ovp detection starts from the beginning of soft-start time tss and ends in shutdown, latch-off, and idle time of hiccup mode caused by other protections. under voltage protection (uvp) the NCP81233 pulls pgood low and turns off both high-side mosfets and low-side mosfets with high impedance in all pwm outputs once vsp-vsn voltage drops below dac-v uvth for more than 5 s. under voltage protection operates in either a hiccup mode or ends in latch-off, which is programmable at mode1 pin as shown in table 11. a normal power up sequence happens after a hiccup interval. to restart the device after latch-off uvp, the system needs to have either vcc5v or en toggled state. uvp detection starts when pgood delay t d_pgood is expired right after a soft start, and ends in shutdown, latch-off, and idle time of hiccup mode. over current protection (ocp) the NCP81233 senses phase current by a differential current-sense amplifier and provides a cycle-by-cycle over current protection for each phase. if ocp happens in all the phases and lasts for more than 8 times of the switching cycle, the NCP81233 turns off both high-side mosfets and low-side mosfets with all pwm outputs in high impedance and enters into a hiccup mode or ends in latch-off, which is programmable at mode1 pin as shown in table 11. a normal power up sequence happens after a hiccup interval. to restart the device after latch-off ocp, the system needs to have either vcc5v or en t oggled state. the part may enter into hiccup mode or latch-off sooner due to the under voltage protection in a case if the output voltage drops down very fast. figure 18. over?current protection and over?temperature protection otp ilmt isp isn isp isn vref ocp otp r t3 r otp2 r otp1 r ntc 10ua r t1 r t2 otp ilmt isp isn isp isn vre f ocp otp r ilim2 r otp2 r otp1 10ua r ilmt1 6 0.6 v v (1) otp configuration 1 (2) otp configuration 2 6 the over -current threshold can be externally programmed at the ilim pin. as shown in figure 18 (1), a ntc resistor r ntc can be employed for temperature compensated over current protection. the peak current limit per phase can be calculated by v isp v isn 1 6 r t3 r t1 r t2 r ntc r t2 r ntc r t3 v ref (eq. 19 ) if no temperature compensation is needed, as shown in figure 18 (2), the peak current limit per phase can be simply set by v isp v isn 1 6 r ilim2 r ilim1 r ilim2 v ref (eq. 20 ) ocp detection starts from the beginning of soft-start time tss, and ends in shutdown and idle time of hiccup mode. over temperature protection (otp) the NCP81233 provides over temperature protection. to serve different types of drmos, one of two internal configurations of otp det ection can be selected at mode2 pin as shown in table 12. with otp configuration 1, as shown in figure 18 (1), the ntc resistor rntc senses the hot-spot temperature and changes the voltage at ilmt pin. both over-temperature threshold and hysteresis are externally programmed at otp pin by a resistor divider. once the voltage at ilmt pin is higher than the voltage at otp pin, the NCP81233 turns off both high-side mosfets and low-side mosfets with all pwm outputs in high impedance and operates in either a hiccup mode or ends in latch-off, which is programmable at mode1 pin as shown in table 11. the controller will have a normal start up after a hiccup interval in condition that the temperature drops below the otp reset threshold. to restart the device after latch-off otp, the system needs to have
NCP81233 www.onsemi.com 39 either vcc5v or en toggled state. the otp assertion threshold votp and reset threshold votp_rst can be calculated by: v otp v ref i otp_hys r otp1 1 r otp1 r otp2 (eq. 21) v otp_rst v ref r otp2 r otp1 r otp2 (eq. 22) the corresponding otp temperature totp and reset temperature t otp_rst can be calculated by t otp 1 ln r ntc_otp
r tnc b 1 25 273.15 273.15 (eq. 23) t otp_rst 1 ln r ntc_otprst
r tnc b 1 25 273.15 273.15 (eq. 24) where: r ntc_otp 1 1 r t_otp r t1 1 r t2 (eq. 25) r ntc_otprst 1 1 r t_otprst r t1 1 r t2 (eq. 26) r t_otp v ref v otp 1 r t3 (eq. 27) r t_otprst v ref v otp_rst 1 r t3 (eq. 28) with otp configuration 2, as shown in figure 18 (2), the NCP81233 receives an external signal vt linearly representing temperature and compares to an internal 0.6 v reference voltage. if the voltage is over the threshold otp happens. the otp assertion threshold v otp and reset threshold v otp_rst in this configuration can be obtained by v t_otp 1 r otp1 r otp2 0.6 (eq. 29) v t_otp_rst 0.6 r otp2 i otp_hys r otp1 0.6 (eq. 30) otp detection starts from the beginning of soft-start time t ss , and ends in shutdown, latch-off, and idle time of hiccup mode. thermal shutdown (tsd) the NCP81233 has an internal thermal shutdown protection to protect the device from overheating in an extreme case that the die temperature exceeds 150 c. tsd detection is activated when vcc5v, en, and drvon are valid. once the thermal protection is triggered, the whole chip shuts down and all pwm signals are in high impedance. if the temperature drops below 125 c, the system automatically recovers and a normal power sequence follows. i 2 c interface control of the NCP81233 is carried out using the i 2 c interface. the NCP81233 is connected to this bus as a slave device, under the control of a master controller. the master controller can start to access the NCP81233 via i 2 c after vcc5v is ready for more than 2 ms. data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high might be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as no acknowledge. the master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the NCP81233, write operations contain one, two or three bytes, and read operations contain one or two bytes. the command code or register address determines the number of bytes to be read or written, see the register map for more information. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed (i.e. command code), and then data can be written to that register or read from it. the first byte of a read or write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a
NCP81233 www.onsemi.com 40 second data byte that is written to the register selected by the address pointer register. this write byte operation is shown in figure 20. the device address is sent over the bus, and then r/ w is set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. ? the read byte operation is shown in figure 21. first the command code needs to be written to the NCP81233 so that the required data is sent back. this is done by performing a write to the NCP81233 as before, but only the data byte containing the register address is sent, because no data is written to the register. a repeated start is then issued and a read operation is then performed consisting of the serial bus address; r/ w bit set to 1, followed by the data byte read from the data register. ? it is not possible to read or write a data byte from a data register without first writing to the address pointer register, even if the address pointer register is already at the correct value. ? in addition to supporting the send byte, the NCP81233 also supports the read byte, write byte, read word and write word protocols. figure 19. send byte d7 d6 d5 d4 d3 d2 d1 d0 e r scl sda start by master ack. by NCP81233 ack. by stop by NCP81233 master frame 1 serial bus address byte 11 000 a1 a0 r/w 1919 frame 2 command code figure 20. write byte scl sda start by master ack. by NCP81233 frame 1 serial bus address byte 11 000 a1 a0 r/w 1919 ack. by NCP81233 frame 2 command code 19 ack. by NCP81233 frame 3 data byte stop by master scl (continued) sda (continued) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
NCP81233 www.onsemi.com 41 figure 21. read byte d7 d6 d5 d4 d3 d2 d1 d0 scl sda start by master ack. by NCP81233 ack. by NCP81233 frame 1 serial bus address byte 11 000 a1 a0 r/w 1919 frame 2 command code d7 d6 d5 d4 d3 d2 d1 d0 scl sda repeated start by master ack. by NCP81233 no ack. by master frame 1 serial bus address byte 11 000 a1 a0 r/w 1919 frame 2 command code stop by master write operations the i 2 c specification defines several protocols for different types of read and writes operations. the ones used in the NCP81233 are discussed in this section. the following abbreviations are used in the diagrams: s?start p?stop r?read w?write a?acknowledge a ?no acknowledge the NCP81233 uses the following i 2 c write protocols. send byte in this operation, the master device sends a single command byte to a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. for the NCP81233, the send byte protocol is used to clear faults. this operation is shown in figure 22. figure 22. send byte command slave addr ess command code a w sa p 24 3 1 5 6 if the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ack and carry out a single byte read without asserting an intermediate stop condition. write byte in this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda and the transaction ends. the byte write operation is shown in figure 23.
NCP81233 www.onsemi.com 42 figure 23. single byte write to a register slave address w a data saa p command code 23 1567 8 4 write word in this operation, the master device sends a command byte and two data bytes to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends the first data byte. 7. the slave asserts ack on sda. 8. the master sends the second data byte. 9. the slave asserts ack on sda. 10. the master asserts a stop condition on sda and the transaction ends. the word write operation is shown in figure 24. figure 24. single word write to a register slave address wa data (lsb) saa command code 23 15678 4 data (msb) ap 910 block write in this operation, the master device sends a command byte and a byte count followed by the stated number of data bytes to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends the byte count n. 7. the slave asserts ack on sda. 8. the master sends the first data byte. 9. the slave asserts ack on sda. 10. the master sends the second data byte. 11. the slave asserts ack on sda. 12. the master sends the remainder of the data byes. 13. the slave asserts an ack on sda after each data byte. 14. after the last data byte the master asserts a stop condition on sda. figure 25. block write to a register slave address w a byte count =n saa command code 23 15678 4 data byte 1 a 9 p a data byte n a data byte 2 10 11 12 13 14 read operations the NCP81233 uses the following i 2 c read protocols. read byte in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserted ack on sda. 6. the master sends a repeated start condition on sda. 7. the master sends the 7 bit slave address followed by the read bit (high). 8. the slave asserts ack on sda. 9. the slave sends the data byte. 10. the master asserts no ack on sda. 11. the master asserts a stop condition on sda and the transaction ends. figure 26. single byte read to a register slave address w a slave address saa command code 23 15678 4 data a p 910 s 11 r read word in this operation, the master device receives two data bytes from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. he master sends a command code. 5. the slave asserted ack on sda. 6. the master sends a repeated start condition on sda.
NCP81233 www.onsemi.com 43 7. the master sends the 7 bit slave address followed by the read bit (high). 8. the slave asserts ack on sda. 9. the slave sends the first data byte (low data byte). 10. the master asserts ack on sda. 11. the slave sends the second data byte (high data byte). 12. the master asserts a no ack on sda. 13. the master asserts a stop condition on sda and the transaction ends. figure 27. single word read to a register slave address w a slave address saa command code 23 15678 4 data (lsb) a 910 s r p a data (msb) 11 12 13 block read in this operation, the master device sends a command byte, the slave sends a byte count followed by the stated number of data bytes to the master device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a repeated start condition on sda 5. the master sends the 7-bit slave address followed by the read bit (high). 6. the slave asserts ack on sda. 7. the slave sends the byte count n. 8. the master asserts ack on sda. 9. the slave sends the first data byte. 10. the master asserts ack on sda. 11. the slave sends the remainder of the data byes, the master asserts an ack on sda after each data byte. 12. after the last data byte the master asserts a no ack on sda. 13. the master asserts a stop condition on sda. figure 28. block write to a command coder slave address w a byte count=n sa slave address 23 15 6 7 8 4 9 p a data byte n a data byte 1 10 11 12 13 s r a alert# signal the NCP81233 has an alert# output to notify the host of fault or warning conditions and also supports the alert response address (ara) protocol. alert# pin is an open-drain output. it is pulled low whenever at least one bit in the status registers is asserted with the following exception, on condition that the corresponding alert is not masked in the mask alert register. bit 6 in status byte and bit 3 in the high byte of status word have no impact on alert#. a broadcast address used by the system host as part of the alert response protocol initiated when a device asserts the alert# signal. the alert response address (0001 100b) can be a substitute for device master capability. the host processes the interrupt and simultaneously accesses all alert# devices through the alert response address. only the device(s) which pulled alert# low will acknowledge the alert response address. the host performs a modified receive byte operation. the 7 bit device address provided by the slave transmit device is placed in the 7 most significant bits of the byte. the eighth bit can be a zero or one. figure 29. alert response address command alert response address srdp n x address a 711711 if more than one device pulls alert# low, the highest priority (lowest address) device will win communication rights via standard arbitration during the slave address transfer. a host which does not implement the alert# signal may periodically access the ara. timeout the NCP81233 includes a timeout feature. if there is no activity for 35 ms, the NCP81233 assumes that the bus is locked and releases the bus. this prevents the device from locking or holding the expecting data. some controllers cannot handle the timeout feature, so it can be disabled. configuration register 1 (0xd1) bit 3 bus_to_en = 1; timeout enabled. bit 3 todis = 0; timeout disabled (default). virus protection to prevent rogue programs or viruses from accessing critical NCP81233 register settings, the lock bit can be set. setting bit 0 of the lock/reset sets the lock bit and locks critical registers. in this mode, certain registers can no longer be written to until the NCP81233 is powered down and powered up again. for more information on which registers are locked see the register map.
NCP81233 www.onsemi.com 44 qfn52 6x6, 0.4p case 485be issue b seating note 4 k 0.10 c (a3) a a1 d2 b 1 14 27 52 e2 52x l bottom view detail c top view side view d a b e 0.10 c pin one location 0.10 c 0.08 c c 40 e a 0.07 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.60 4.80 e 6.00 bsc 4.80 e2 4.60 e 0.40 bsc l 0.25 0.45 l1 0.00 0.15 note 3 plane dimensions: millimeters 0.25 4.80 0.40 4.80 52x 0.63 52x 6.40 6.40 *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* detail b l1 detail a l alternate terminal constructions l 0.30 ref pitch 52x pkg outline l2 0.15 ref l2 detail c 8 places l2 detail a detail d 8 places 0.11 0.49 detail d on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81233/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

▲Up To Search▲

Price & Availability of NCP81233

	To Download NCP81233 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .